A bus specification for I2C systems is described in detail in “THE I2C-BUS SPECIFICATION, VERSION 2.1, JANUARY 2000”, which is incorporated herein by reference.
In the “slave mode” of a device of an I2C device, the serial clock signal SCK usually is automatically “stretched” after reception or transmission of a data byte by the I2C slave device. The automatic stretching of the clock signal SCK is required so that the slave device can read data that is received by it or prepare a new byte for transmission by the slave device. However, a problem of conventional I2C systems is that if a CPU (central processing unit) device of an I2C device in its slave mode is fast enough to process the data to be received or transmitted within the present byte transaction, the automatic stretching actually can be considered to be unnecessary and therefore to unnecessarily slow down the I2C bus speed.
Any time a prior art I2C device is in its slave mode, it “stretches” the clock signal (also referred to simply as the “clock”) by holding the SCK clock conductor at a low level for a sufficiently long amount of time to allow the I2C device to perform its assigned function. (Note that an I2C device functioning in its slave mode is often referred to simply as a “slave”, and that an I2C device functioning in its master mode is often referred to simply as a “master”.) The amount of time that the clock SCK is stretched depends on the CPU of the slave and what it has to accomplish. The CPU of the slave receives data from an I2C device that is in its master mode, so once the slave receives the data from the master, the slave stretches the clock SCK to notify the master to not send any more data until the slave “releases” the clock signal conductor. The data received by the slave is shifted into a shift register. After the shift register is full, no more data can be received from the master until the data in the shift register is removed (which can be accomplished in various ways).
Every I2C device to which the present invention pertains needs to have a CPU. (However, some “stand-alone” I2C devices, such as an ADC, do not include a CPU). I2C devices to which the present invention pertains need to be able to operate in a slave mode (but not necessarily in a master mode). I2C devices are usually implemented at a certain protocol level that may be dependent on their main intended use. For example, an I2C device may be used in conjunction with an ADC so that the ADC performs an analog-to-digital conversion and the digital result is stored into the I2C device and then is transmitted via the SDA conductor when the master sends SCK clock pulses. In this case, the master would know that it wants to read, for example, three bytes of data from the slave (because the master knows that the slave is a 24 bit ADC). So the master would send a start condition on the SCK/SDA bus and send the serial clock SCK as needed in order to send three bytes on the SDA conductor, and then send a stop condition on the SCK/SDA bus. In this case, there would be no need for the slave to stretch serial clock SCK. If the master did not execute a read operation before the subject slave performed another analog-to-digital conversion while the slave still has unread data, the “unread” data could be cached, and later refreshed with the “new” conversion data. Note that the I2C device implementation in this example is very specific to its intended use in conjunction with the particular 24-bit ADC.
Thus, it is not always necessary for an I2C slave device (in its receive mode) to stretch the clock. In the foregoing 24-bit ADC example, it is not necessary to stretch the clock because if the first byte of conversion data is available, then all of the three bytes of conversion data will be available, so the slave will not need to implement a stretch of SCK. Therefore, the master can continue to generate the serial clock signal SCK and can read all three bytes without waiting for a STRETCH_RELEASE control signal from the slave. Or, if the master polls components of the slave, it might not need to stretch the clock. Generally, the CPU of an I2C slave device knows when it is finished with the present task and can send out a STRETCH_RELEASE control signal. Whether the slave needs to send a STRETCH_RELEASE control signal to the master depends on the specific situation. However, it should be understood that in most cases the slave actually does stretch the clock SCK.
Thus, there is an unmet need for an I2C system which can increase the data throughput rate on the I2C bus.
There also is an unmet need for an I2C system which avoids the need for a slave device to stretch the clock SCK if the function of the slave device can be completed within the present byte time interval.